Re: Gwydion & threads

[Eric Gouriou <address@hidden>]

Eric Gouriou wrote:
[...]
>   The ISA I am most familiar with (IA64) does not
> necessitate any OS support to specify memory ordering
> constraints. I believe that's the norm, rather than the
> exception.
> 
>   From memory:
>   ldN  -> N bytes load, no memory ordering constraint, N=1,2,4,8
>   stN  -> N bytes store, no memory ordering constraint, N=1,2,4,8
> 
>   ldN.acq  -> N bytes ordered load, acquire semantics (aka read fence)
>   stN.rel  -> N bytes ordered store, release semantics (aka write fence)
> 
>   mf       -> memory fence (aka read/write fence)
> 
> Roughly:
>   A read fence ensures that any previous read from the same
> thread occur before this instruction.

 Ooops, correction: a read fence guarantees that any memory
reference downstream from the fence cannot see "older" values.

 Pseudo C/assembly, very artificial example:
---------
  struct {
    uint32_t  empty;
    int       value;
  } foo;

 Thread A:                              Thread B:
   do                                       ...
    ld.acq  empty? = ["& foo.locked"]      st     ["&foo.value"] = new_value
    ld      val    = ["& foo.value"]       st.rel ["&foo.empty"] = 0 "false"
   while (empty?)
---------
 Here we are guaranteed that Thread A val will contain new_value,
not the previous value.

 Apologies for this error, working with weakly ordered memory models
necessitates a bit of rigor, and it was clearly lacking here :-(.

 Eric

-- 
Eric Gouriou                             egouriou@cup.hp.com