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Re: Diversity - existence, value, and pursuit.

At 02:08 PM 12/3/2001 -0500, Scott McKay wrote:
>  (2) We managed to fit most of our emulator entirely in the chip's 
> instruction
>    cache, meaning that instead of an application suffering from both 
> instruction
>    and data fetch stalls, we suffered only from data cache stalls.  This 
> meant
>    that we ran most code, essentially, without stalls.  (To be sure, we
>    optimized the hell out of our VM; the main instruction dispatch loop had
>    an average execution of 11 instructions in 6 cycles on DEC Alpha, and
>    if we had a "tail call" architecture, we could have done much better.)
>The second point is very important in modern OO programs, whose instruction
>sequences are very far from straight line.

This is something I'm counting on for Parrot, and something I didn't get 
into with my slides at LL1. Blowing L1 cache is really expensive. On the 
other hand, blowing your pipeline can be as expensive in some processors, 
so you end up making the tradeoff of small code with lots of conditionals 
(which will fit in cache but blow the pipeline a lot) or larger code with 
less conditionals (which blows cache more but the pipeline less). I'm 
hoping that the mainline processors at parrot release time will have large 
enough L1 caches that my choice (the second) will get us better performance.


--------------------------------------"it's like this"-------------------
Dan Sugalski                          even samurai
dan@sidhe.org                         have teddy bears and even
                                      teddy bears get drunk