CPS with Multiple Stack Machine Architectures

["Peter J. Wasilko, Esq." <address@hidden>]

Greetings All,

> Second of all, his (trivially googlable) explanation of CPS is here:
> http://www.sidhe.org/~dan/blog/archives/000185.html
> 

    Dan's Blog made some interesting points that seemed to suggest that
some of the challenges of building CPS-based language implementations
were related to today's dominant chip architectures' having a single
stack and heap in the same address space.
    
    In "Stack Computers: the new wave"
http://www-2.cs.cmu.edu/~koopman/stack_computers/ Philip J. Koopman,
Jr. describes some stack computer architectures with multiple hardware
stacks and large stack memories.
    
    Would it be easier to do a CPS-based language implementation in such
an environment?

    Koopman's book is a bit old (as far as its publication date goes),
but a fascinating read none the less.

    Does anyone know what the current state of the art is for such
designs?

Regards,

Peter


_________________________________________________________________

Peter J. Wasilko, Esq.
     J.D., LL.M.               

Executive Director, The Institute for End User Computing, Inc.

Visit us on the web at: http://www.ieuc.org

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Its time to abandon brittle architectures with poorly factored
interfaces, gratuitous complexity, and kludged designs dominated
by sacrifices on the altar of backwards compatibility.

Such artifacts are vulnerable to cyber-attack, weigh down the
economy costing trillions of dollars in lost productivity, and
suffer from an impoverished conceptual model that lacks the
integration and elegance needed to empower end users to
get the most from advanced applications in the future.

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