#;text-till-end-of-line
: Infrastructure<block-name>
: Blocks and Chips=
: Functional Designarithmetic-shift
: Functional Designarray-ref
: Functional Designarray-set
: Functional Designash
: Functional Designbit-field
: Functional Designbitwise-if
: Functional Designbooleans-to-number
: Functional Designcheck=
: Simulation Outputcomment
: InfrastructureCompany-stamp:
: InfrastructureConfiguration-stamp:
: Infrastructurecopy-bit
: Functional Designcopy-bit-field
: Functional Designcreate-board
: Infrastructuredefine-synchronous-system
: Blocks and Chipsfifo:clear
: Modelsfifo:empty?
: Functional Designfifo:first
: Functional Designfifo:full?
: Functional Designfifo:fullness
: Functional Designfifo:insert-last
: Functional Designfifo:remove-first
: Functional Designlogand
: Functional Designlogbit?
: Functional Designlogior
: Functional Designlognot
: Functional Designlogtest
: Functional Designlogxor
: Functional Designmake-fifo
: Modelsmake-ram
: Modelsmake-ram-array
: Modelsnumber-check
: Functional Designnumber-or
: Functional DesignRevision-stamp:
: Infrastructuresynch:chat
: Simulation Outputsynch:declare
: Macros for Signals and Pinssynch:defcheck
: Macros for Signals and Pinssynch:define
: Macros for Signals and Pinssynch:define-bus
: Signals and Pinssynch:define-pin
: Signals and Pinssynch:define-signal
: Signals and Pinssynch:definput
: Macros for Signals and Pinssynch:defmacro
: Macros for Signals and Pinssynch:defreginput
: Macros for Signals and Pinssynch:defshare
: Macros for Signals and Pinssynch:error
: Simulation Outputsynch:fifo
: Modelssynch:info
: Simulation Outputsynch:insert-check
: Signals and Pinssynch:pre
: Macros for Signals and Pinssynch:print
: Simulation Outputsynch:register-block
: Blocks and Chipssynch:register-ptag
: Blocks and Chipssynch:set!
: Macros for Signals and Pinssynch:set/reset!
: Macros for Signals and Pinssynch:warn
: Simulation OutputTime-stamp:
: Infrastructuretranslate
: Translationzero?
: Functional Design*board*
: Infrastructure*design*
: Infrastructureprint-chat
: Simulation Outputprint-timing
: Simulation Outputsynch:count
: Simulation Output