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SELECTED PEER-REVIEWED JOURNALS
[ J6 ] E. Taheri, M. Isakov, A. Patooghy, M. A. Kinsy: “Addressing a New Class of Reliability Threats in 3-Dimensional Network-on-Chips”. In the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.[Paper] [BibTex]

[ J5 ] T. Yang, Y. Wei, Z. Tu, H. Zeng, M. A. Kinsy, N. Zheng and P. Ren: “Design Space Exploration of Neural Network Activation Function Circuits”. In the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.[Paper] [BibTex]

[ J4 ] M. A. Kinsy, L. Bu, M. Isakov and M. Mark: “Designing Secure Heterogeneous Multicore Systems from Untrusted Components”. Cryptography, vol. 2, iss. 3, no. 12, 2018.[Paper] [BibTex]

[ J3 ] P. Ren, M. Kinsy, and N. Zheng: “Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies.” In the Transactions on Computers (TC), March 2016.[Paper] [BibTex]

[ J2 ] P. Ren, X. Ren, S. Sane, M. Kinsy, and N. Zheng: “Deadlock-Free and Connectivity- Guaranteed Methodology for Achieving Fault-tolerance in On-chip Networks.” In the Transactions on Computers (TC), February 2016.[Paper] [BibTex]

[ J1 ] M. Kinsy, M. H. Cho, T. Wen, M. Lis , G. E. Suh, M. Dijk, and S. Devadas: “Optimal and Heuristic Application-Aware Oblivious Routing.” In the Transactions on Computers (TC), January 2013.[Paper] [BibTex]

 SELECTED PEER-REVIEWED CONFERENCES
[ C15 ] M. Isakov, L. Bu, H. Cheng, and M. A. Kinsy: “Preventing Neural Network Model Exfiltration in Machine Learning Hardware Accelerators”. In the 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2018.[Paper] [BibTex]

[ C14 ] L. Bu and M. Kinsy: “Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions”. In the International conference on Field Programmable Logic and Applications (FPL), August 2018.[Paper] [BibTex]

[ C13 ] M. Isakov, A. Ehret and M. Kinsy: “ClosNets: Batchless DNN Training with On-Chip A Priori Sparse Neural Topologies”. In the International conference on Field Programmable Logic and Applications (FPL), August 2018.[Paper] [BibTex]

[ C12 ] J. R. Doppa, R. G. Kim, M. Isakov, M. A. Kinsy, H. Kwon and T. Krishna: “Adaptive Manycore Architectures for Big Data Computing.” In the International Symposium on Networks-on-Chip (NOCS), October 2017.[Paper] [BibTex]

[ C11 ] L. Bu, H. D. Nguyen, and M. A. Kinsy: “RASSS: A perfidy-aware protocol for designing trustworthy distributed systems.” In the 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 2017.[Paper] [BibTex]
Best Best Student Paper Award and Best Paper Nominee

[ C10 ] M. Kinsy, S. Khadka, M. Isakov and A. Farrukh: “Hermes: Secure Heterogeneous Multicore Architecture Design.” In the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017.[Paper] [BibTex]

[ C9 ] M. Kinsy, I. Celanovic, O. Khan, and S. Devadas: “MARTHA: Architecture for Control and Emulation of Power Electronics and Smart Grid Systems.” In IEEE International Conference on Design, Automation and Test in Europe (DATE), March, 2013.[Paper] [BibTex]

[ C8 ] M. Kinsy, M. Pellauer, and S. Devadas: “Heracles: A Tool for Fast RTL-Based Design Space Exploration of Multicore Processors.” In Proceedings of the 21st International Symposium on Field-Programmable Gate Arrays (FPGA), February 2013.[Paper] [BibTex]

[ C7 ] M. Kinsy, O. Khan, I. Celanovic, M. Dusan, N. Celanovic, and S. Devadas: “Time- Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems.” In Proceedings of the 32nd Real-Time Systems Symposium (RTSS), December 2011.[Paper] [BibTex]

[ C6 ] M. Kinsy, M. Pellauer, and S. Devadas: “Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System.” In Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL), September 2011.[Paper] [BibTex]
BestTools and Open-Source Community Service Award

[ C5 ] M. Pellauer, M. Adler, M. Kinsy, A. Parashar, and J. Emer: “HAsim: FPGA-based high detail multicore simulation using time-division multiplexing.” In Proceedings of the 17th International Symposium on High Performance Computer Architecture (HPCA), February 2011.[Paper] [BibTex]

[ C4 ] M. H. Cho, M. Lis, K. S. Shim, M. Kinsy, T. Wen, and S. Devadas: “Oblivious Routing in On-Chip Bandwidth-Adaptive Networks.” In Proceedings of the Parallel Architectures and Compilation Techniques (PACT), September 2009.[Paper] [BibTex]

[ C3 ] M. Kinsy, M. H. Cho, T. Wen, G. E. Suh, M. Dijk, and S. Devadas: “Application-Aware Deadlock-Free Oblivious Routing.” In Proceedings of the International Symposium on Computer Architecture (ISCA), June 2009.[Paper] [BibTex]

[ C2 ] K. S. Shim, M. H. Cho, M. Kinsy, T. Wen, M. Lis , G. E. Suh, and S. Devadas: “A Comparison of Static and Dynamic Virtual Channel Allocation in Oblivious Routing.” In Proceedings of the International Symposium on Networks-on-Chip (NOCS), May 2009.[Paper] [BibTex]

[ C1 ] M. H. Cho, C-C. Cheng, M. Kinsy, G. E. Suh, and S. Devadas: “Diastolic Arrays: Throughput-Driven Reconfigurable Computing.” In Proceedings of the International Conference on Computer-Aided Design (ICCAD), November 2008.[Paper] [BibTex]

FULL PUBLICATION LIST

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