Contact Information

MIT CSAIL
32 Vassar St, 32-G864
Cambridge, MA 02139

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Education

Ph.D., Electrical Engineering, University of Illinois Urbana-Champaign, 1979
M.S., Electrical Engineering, Purdue University, 1975
B.S., Electrical Engineering, Purdue University, 1974

Biography

Joel Emer is a Professor of the Practice at MIT's Electrical Engineering and Computer Science Department (EECS) and a member of the Computer Science and Artificial Intelligence Laboratory (CSAIL). He is also a Senior Distinguished Research Scientist at Nvidia in Westford, MA, where he is responsible for exploration of future architectures as well as modeling and analysis methodologies. Prior to joining NVIDIA, he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research. Previously he worked at Compaq and Digital Equipment Corporation (DEC).

Dr. Emer has held various research and advanced development positions investigating processor micro-architecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. He has also been recognized for his contributions in the advancement of simultaneous multi-threading technology, analysis of the architectural impact of soft errors, memory dependence prediction, pipeline and cache organization, performance modeling methodologies and spatial architectures.

Dr. Emer holds over 25 patents and has published more than 60 papers.

Research Interests

Research Honors

Courses Taught

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Journal Publications

Conference Publications

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