Joel S. Emer-profile picture


Joel Emer is a Professor of the Practice at MIT's Electrical Engineering and Computer Science Department (EECS) and a member of the Computer Science and Artificial Intelligence Laboratory (CSAIL). He is also a Senior Distinguished Research Scientist at Nvidia in Westford, MA, where he is responsible for exploration of future architectures as well as modeling and analysis methodologies. Prior to joining NVIDIA, he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research. Previously he worked at Compaq and Digital Equipment Corporation (DEC).

Dr. Emer has held various research and advanced development positions investigating processor micro-architecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. He has also been recognized for his contributions in the advancement of simultaneous multi-threading technology, analysis of the architectural impact of soft errors, memory dependence prediction, pipeline and cache organization, performance modeling methodologies and spatial architectures.

Dr Emer received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. He earned a doctorate under the direction of Profressor Edward Davidson in electrical engineering from the University of Illinois in 1979.

Dr. Emer holds over 25 patents and has published more than 60 papers.

For some more backgound on my career and some of my research philosoply, there is the Rau Award acceptance speech I gave at MICRO in 2023 and the YARCH keynote speech I gave at the 2021 Young Architects Workshop in 2021.

I also co-advise a number of students with Professor Vivienne Sze, and the work from that collaboration is described at the Emze group website.


  • Ph.D., Electrical Engineering, University of Illinois Urbana-Champaign, 1979
  • M.S., Electrical Engineering, Purdue University, 1975
  • B.S., Electrical Engineering, Purdue University, 1974

Research Interests

  • Accelerator Architectures for Sparse Computation
  • Accelerator Architectures for Deep Learning
  • Spatial Processing Architectures
  • Parallel Processor Architectures
  • Computer Memory Hierarchy Design
  • Architecture and Analysis of Processor Reliability
  • Performance Modeling Methodologies
  • Programming Environments for FPGA-based Applications