Honors

Research Honors

• Paper "TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators" selected as an IEEE Micro "Top Picks in Computer Architecture" honorable mention for 2023.
• Received IEEE Computer Society B. Ramakrishna Rau award for "For pioneering contributions to microarchitectural analysis, microarchitecture features, and for bringing clarity to the field with fundamental concepts and terminology." [video]
• Paper "Understanding Error Propagation in Deep-Learning Neural Networks Accelerators and Applications" selected a 2023 IEEE Top Picks in Test and Reliability.
• Five papers selected for inclusion in ISCA@50 25-year retrospective 1996-2020, 2023.
  • "Eyeriss: a spatial architecture for energy-efficient dataflow for convolutional neural networks" [retrospective]
  • "Scheduling heterogeneous multi-cores through performance impact estimation (PIE)" [retrospective]
  • "High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)" [retrospective]
  • "Adaptive Insertion Policies for High Performance Caching" [retrospective]
  • "Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor" [retrospective]
• Recognized for having the most highly cited papers in the first 50 years of ISCA (tied with Norm Jouppi), 2023. [blog post]
• Paper "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor" selected for SIGMICRO Test of Time Award, 2022.
• Paper "Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling" selected for SIGMICRO Distinguished Artifact Award, 2022.
• Paper "Casa: End-to-end quantitative security analysis of randomly mapped caches" selected as an honorable mention in the Top Picks in Hardware and Embedded Security, 2022.
• Received the IASED Lifetime Achievement Award for 2022.
• Paper "A 0.128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16nm" selected as JSSC best paper, 2021.
• Elected a member of the National Academy of Engineering "For quantitative analysis of computer architecture and its application to architectural innovation in commercial microprocessors", 2020.
• Paper "Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture" selected for best paper award at Micro 2019 and as a ACM "Research Highlight" for 2020.
• Paper "Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration" selected as an IEEE Micro "Top Picks in Computer Architecture" honorable mention for 2020.
• Paper "ExTensor: An Accelerator for Sparse Tensor Algebra" selected as an IEEE Micro "Top Picks in Computer Architecture" honorable mention for 2020.
• Paper "Hardware for Machine Learning: Challenges and Opportunities" selected as best invited paper at CICC for 2017.
• Paper "Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks" selected for IEEE Micro "Top Picks in Computer Architecture" for 2016.
• Paper "Data-Centric Execution of Speculative Parallel Programs" selected for IEEE Micro "Top Picks in Computer Architecture" honorable mention for 2016.
• Paper "A Scalable Architecture for Ordered Parallelism" selected for IEEE Micro "Top Picks in Computer Architecture" for 2015.
• Named to the Micro Hall of Fame, 2015.
• Paper "Using In-flight Chains to Build a Scalable Cache Coherence Protocol" selected for ACM Computing Reviews: Notable computing books and articles award for 2013.
• Paper "Triggered Instructions: A Control Paradigm for Spatially-Programmed Architectures" selected for IEEE Micro "Top Picks in Computer Architecture" for 2013.
• Recipient of University of Illinois Electrical and Computer Engineering Distinguished Alumni Award "For advancing the art of performance modeling and measurement of microarchitectures and for contributions to the design of leading-edge microprocessors ", 2011.
• Paper "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multitheading Processor" selected for ACM/SIGARCH - IEEE-CS/TCCA: Most Influential Paper Award, 2011.
• Named to the HPCA Hall of Fame, 2011.
• Recipient of Purdue University Outstanding Electrical and Computer Engineer Alumni Award, 2010.
• Recipient of ACM/IEEE-CS Eckert-Mauchly Award "For pioneering contributions to performance analysis and modeling methodologies; for design innovations in several significant industry microprocessors; and for deftly bridging research and development, academia and industry", 2009.
• Paper "Adaptive Insertion Policies for High Performance Caching" selected for IEEE Micro "Top Picks in Computer Architecture" for 2008.
• Named to the ISCA Hall of Fame, 2005.
• Named Fellow of the Association for Computing Machinery "For contributions to computer architecture and performance analysis.", 2004.
• Paper "Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor" selected for IEEE Micro "Top Picks in Computer Architecture" for 2004
• Named Fellow of the Institute of Electrical and Electronics Engineers "For contributions to computer architecture and quantitative analysis of processor performance", 2004.
• Paper "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor" selected for IEEE Micro "Top Picks in Computer Architecture" for 2003.
• Paper "A Characterization of Processor Performance in the VAX-11/780" selected for reprint in "25 Years of the International Symposium on Computer Architecture", 1999. [retrospective]