Scheme for Engineering 1997

It has been a hectic 2 years since I wrote Scheme for Electronic Design (1995) and Scheme for Software Engineering (1995). The board (and driver) has been used very successfully in several products.


During 1996, I added new features (to the programmable logic) and optimized the decompression processors to reach the plateau of "no wasted states", i.e. output is generated at clock speed. I also spent months hunting a bug stemming from an unannounced behavior change in one vendor's components; I had noticed the change early, but modeled it incorrectly in the simulator.

SIMSYNCH worked so well that I applied it to the rest of the design. I wrote a parser to generate SIMSYNCH equations from logic-compiler listings. I also wrote a Scheme program to find (from the listings) and tabulate pin-number changes which some logic `fitters' make.


This year I designed and debugged the successor decompression board. During development, I rewrote SIMSYNCH to improve simulation speed. It should now be possible to save simulation state to a file, although I haven't used this feature yet. I wrote models for JTAG and incorporated them into the simulation. I converted SIMSYNCH to use a SLIB relational database. SIMSYNCH now supports multiple synchronous blocks (with independent clocks) implemented within one device (while supporting synchronous blocks spread among multiple devices).

The 1997 board incorporated much of the previous board's programmable logic equations into a different device. I fit this logic (but none of the new glue) into the new device before sending the schematics to layout; but I did not get to finalizing the equations until the boards were assembled. This code, containing the bulk of the design's complexity, worked without problem.

I have kept the 1995 design (version 212) current with SIMSYNCH and it still compiles to working firmware. This provides a good regression test against changes to SIMSYNCH, device models, or driver software.

The Joy of Batch

In my designs, the compilation date, configuration, and version are captured automatically and used to generate JTAG USER-id fields. Similarly, I reverse-engineered the schematic format enough to enable a small Scheme program to list and change date, revision number, and sheet order of sheets in the design.

I wrote MS-DOS and SCM scripts to automate logic compilation and fitting, schematic checking, conversion of drawings, net-list and bill-of-materials creation, pin-number checks and schematic symbol creation, and driver translation (to C) and compilation.

All this automation not only lets me avoid the buggy GUI programs so many vendors wrap around their programs, it also relieves my memory of the burden of remembering how to perform these tasks. But nicest of all, I don't have to stare at the screen waiting for one phase of a compilation to complete in order to click on the next.

What Have We Learned?

We are currently building the next generation design and tools. This design will be more than 5 times the complexity of the current board, use higher clock rates, have more parallelism, support higher data rates, perform 2-dimensional image decompression, and incorporate new parts and vendors. SIMSYNCH will be enhanced to provide higher level components such as adders and multipliers.

What Remains to be Done?

In these two designs, the checks for bus fights (signal driven by multiple outputs at once), floating (undriven) signals, and setup and hold times, were written by hand. This was sufficient for the first design; but the current one has more numerous configurable data paths. This, in combination with my delaying writing these checks in my haste to complete the schematics, produced some serious problems which simulation did not detect.

When Will SIMSYNCH be Released?

The SIMSYNCH Digital Logic Simulation System is now available.

Copyright 1997 Aubrey Jaffer

I am a guest and not a member of the MIT Computer Science and Artificial Intelligence Laboratory.  My actions and comments do not reflect in any way on MIT.
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