The SIMSYNCH Digital Logic Simulator

Current Version Released Terms
1c5 2010-06-30 GPL 3.0

SIMSYNCH is a simulator for digital electronics at scales from chip to board.
The design files are comprised of Scheme definitions and expressions. These design files can be run as a Scheme program at high speed. The design files can also be translated into formats suitable for logic compilers (MACHXL and Verilog).

SIMSYNCH simulates blocks of synchronous logic, signals whose states change simultaneously on a clock signal transition. Each block also has a reset signal, which forces all signals to the state specified in the design file. SIMSYNCH can simultaneously simulate multiple blocks with different clocks and resets. Devices can contain multiple blocks; Blocks can span multiple devices.

SIMSYNCH is an application of the SCM Scheme implementation.


Quick Start



Included in the SimSynch distribution is fifo8, a trivial design example of an 8-word FIFO with a testbench demonstrating its operation. The transcript shows 8 bytes being written to the empty FIFO from cycle 05 through cycle 0c; and 8 bytes are read from cycles 19 through 20. Several files are generated by by running fifo8.scm:

SIMSYNCH Development

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Copyright © 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2008, 2010 Aubrey Jaffer

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