The design files are comprised of Scheme definitions and expressions.
These design files can be run as a Scheme program at high speed. The
design files can also be translated into formats suitable for logic
compilers (MACHXL and Verilog).
SIMSYNCH simulates blocks of synchronous logic, signals whose states
change simultaneously on a clock signal transition. Each block also
has a reset signal, which forces all signals to the state specified
in the design file. SIMSYNCH can simultaneously simulate multiple
blocks with different clocks and resets. Devices can contain
multiple blocks; Blocks can span multiple devices.
SIMSYNCH is an application of the 