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Potential Uses of Dynamically Reconfigurable Analog Circuits

Faculty: Una-May O'Reilly
Students: Varun Aggarwal, Meng Mao (UAP)
Status: Active, within EVO-DesignOpt and recruiting new students
Alumni: Michael Terry (Raytheon), Matthew Farrell, Jonathan Marcus
Opportunities: UROP summer, '06 and Fall-Winter '06-'07, M.Eng '06-'07, UAP '06-'07
Reconfigurable digital circuits are ubiquitous in the world of digital electronics due to the advent of Field Programmable Gate Arrays (FPGA). They have their own place, parallel to ASICs, in industry and academia. Industry uses FPGAs because they enable short time-to-market, fast debugging of prototypes and field upgrades. In terms of cost, they break even at a lower quantity than an ASIC. Within academia, and now at the point of technology transfer, the dynamic reconfigurability of an FPGA has enabled and promoted a whole body of research in custom-computing and fault tolerance.

Do parallel advantages exist for reconfigurable analog circuits? Do reconfigurable analog circuits have practical uses? To enable practical use, what design approaches and complementary algorithms should be developed? These are the questions this research project sets out to ask.

The questions of potential use for analog reconfigurability differ from those of the digital domain. This stems from the non-existence of an abstracted universal block which could be used to systematically realize  analog circuits (such as  the concept of gates in digital design). Different reconfigurable platforms use different building blocks such as Anadigm's FPAA (switched-capacitor circuits), ispPAC (opamps and passive components) and FPTAs (transistors). The choice of blocks trades off among flexibility, amount of resources and reliability [3]. The smaller size of FPAAs (lesser number of resources) and affect of interconnect parasitics are issues of major concern. Due to these reasons, each cannot realize a wide spectrum of analog circuits and is not well-suited for general prototyping. The non-existence of accurate simulators for FPAAs (including parasitic and interconnect affects) makes their integration in design flow difficult. Given this situation, we are exploring the answers to two questions, i. Do reconfigurable circuits have niche applications?, ii. What kind of methodology and algorithms can preclude the need of accurate simulators?

One potential application of an analog reconfigurable circuit is to use it within a larger system as a system level tuning component. For example, a plant-controller system requires the controller's parameters to be tuned or an equalizing filter requires tuning for a varying channel. Such controllers or filters could be analog reconfigurable circuits but not static ASICs. Presently, these problems are addressed by using a DSP processor coupled with ADCs (Analog to Digital Converters) and DACs (Digital to Analog Converters). While this solution works, it comes at the cost of higher power and lower speed. A reconfigurable analog circuit would significantly reduce the power consumption because, if it is an FPAA, it will use less power than a DSP [1], and, because it will eliminate the power costs of the ADCs and DACs. A valuable additional improvement to this system is to pair it with a self-tuning module to eliminate the need for a human designer to iteratively tune it.

This project has already developed a complete framework for self-tuning analog controllers. The framework alleviates the need to model either the environment or the system itself (equivalent to accurate simulators) by using model-free algorithms such as Evolutionary algorithms. To demonstrate the framework we developed a self-tuning analog PID controller that used the Anadigm FPAA as the reconfigurable circuit [2]. We are interested in exploring other such domains, where the system has to tune according to the environment. This notion extends to adaptive circuits, which re-tune themselves according to a changing environment.We are also interested in exploring the use of a reconfigurable part in ASIC to facilitate Design for Yield and Design for Low Power. Conventionally, correction after fabrication/design for highly accurate systems is facilitated by laser-trimming. We want to explore the option of embedded electronic reconfigurability for accuracy-critical components of the circuits. These components can then be tuned automatically by a model-free method after fabrication, which would alleviate measurement overheads. Design for yield and low power design are in trade-off (in a way!), because high yield systems need larger components. but larger components dissipate more power. If reconfiguration after fabrication can address yield with lower-valued components (as in [4]), the trade-off relation is decoupled. Thus we believe that reconfiguration after fabrication has the potential of improving yield, power and resulting in more accurate systems.


We will consider reconfigurable analog circuits independent of the technologies with which they can be instantiated: printed circuit board, field programmable analog array (FPAA) or silicon. Our studies will use simulation, PCBs, FPAAs and may even venture into design for silicon. Currently we have constructed a testbench comprising an Anadigm Field Programmable Analog Array (FPAA) that is automatically reconfigured by a circuit design and optimization algorithm running on a computer. The system, which we christened GRACE (Generative Robust Analog Circuit Exploration), is shown in Figure 1. In this configuration, the FPAA acts as a controller to a plant and forms a closed loop system. The circuit design and optimization algorithm runs on a PC and its objective is to generate a controller that controls the output to follow the input. To test candidate solutions, the algorithm generates a reference signal that is converted to an analog signal by an ADC and sent as the input to the closed loop system. The reference signal and the output of the closed loop system are digitized (in DAQ) and fed back to the algorithm. The algorithm optimizes an objective function defined on these two signals. In [3], we showed how by using Genetic Programming and a new optimization algorithm, Particle Swarm Optimization, the algorithm could both invent a topology for the controller and size it.

Figure 1: GRACE: An Analog Reconfigurable System


Subsequently we have used GRACE to develop a self-tuning analog PID controller that we believe is the first of its kind (see [2]). The system captures the traditional advantages of an analog system such as low power, elimination of quantization noise, high speed and large bandwidth. Using an online model-free tuning technique, we overcome the problem of feasibility and realizability of the circuits associated with analog reconfigurable arrays. The system can self-tune for a given plant and perform better than a hand-tuned solution. Future directions in this research are in the context of adaptive controllers and a custom-made reconfigurable PID controller chip with low power requirements that suits portable applications such as robots and space systems.

GRACE is a generic platform for design of self-tuning and adaptive analog circuits. We are working on conceptualizing other potential applications of GRACE. We plan to test out ideas of reconfigurability in ASICs through simulations.


[1] T.S. Hall, C.M. Twigg, J. D. Gray, P. Hasler, D. V. Anderson. Large-scale field-programmable analog arrays for analog signal processing. IEEE Transactions on Circuits and Systems (Part I) , 52(11), pp. 2298- 2307, Nov. 2005
[2] V. Aggarwal,  M.  Mao, U.M. O'Reilly, A Self-Tuning analog PID controller.
[3] M. Terry, J. Marcus, M. Farrell, V. Aggarwal and U M O'Reilly. GRACE: Generative Robust Analog Circuit Exploration. Accepted in The 9th European Conference on Genetic Programming, EuroGP 2006
[4] M. Murakawa, T. Adachi, Y. Nino, Y. Kasai, E. Takahashi, K. Takasuka and T. Higuchi. An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions. In IEEE Journal of Solid-State Circuits , Vol. 38 No. 3, pp. 495-502, 2003