I'm an Nth-year (N≈5.5) PhD student at the Massachusetts Institute of Technology, and I'm advised by Professor Daniel Sanchez. I received my Master's degree at MIT in 2016 and my Bachelor's degree at the University of California, Berkeley in 2014. I attended Troy High School in Fullerton, California.
My research focuses on exploiting fine-grain pipeline parallelism in challenging applications (irregular memory accesses; quickly-varying work) at the core microarchitecture level. My past work includes porting Linux to the then-nascent RISC-V architecture, scalable cache coherence protocols, and research on vector-style data-parallel accelerators.
In what time remains I develop a place-and-route tool for Minecraft circuits, maintain (and ride) vintage Schwinn bicycles, and dance the Lindy Hop.
To contact me, join my initials (qmn) and mit.edu with the @ sign.
Publications here are for academic or personal uses only. The journey of a thousand publications begins with a single workshop.
- Pipette: Improving Core Utilization on Irregular Applications through Intra-Core Pipeline Parallelism, Quan Nguyen, Daniel Sanchez, Proceedings of the 53rd International Symposium on Microarchitecture (MICRO-53), Athens, Greece, October 2020. [pdf] [slides pdf]
- Towards Thousand-Core RISC-V Shared Memory Systems, Quan Nguyen, the 5th RISC-V Workshop, Mountain View, CA, November 2016. [youtube]
- Synchronization in Timestamp-Based Cache Coherence Protocols, Quan Nguyen, S.M. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, June 2016. [pdf]
- A Case for MVPs: Mixed-Precision Vector Processors, Albert Ou, Quan Nguyen, Yunsup Lee, Krste Asanović, 2nd International Workshop on Parallelism in Mobile Platforms (PRISM-2) at the 41st International Symposium on Computer Architecture (ISCA-41), Minneapolis, MN, June 2014. [pdf]