Alexander Matveev Homepage
- My main research area is highly-concurrent performance-engineered multi-core systems. In particular, fast frameworks for concurrency and synchronization, hardware-software transactional memory, and scalable garbage collectors.
- Currently, I'm working on fast multicore systems for executing machine learning algorithms. As part of this work, I had build a big-data high-throughput connectomics pipeline, which is intended to analyze terabytes of brain electron microscopy image data to extract its fine-grained connectivity. This project was done in collaboration with neurobiologists at MIT and Harvard.
- A. Matveev, Y. Meirovitch, H. Saribekyan, W. Jakubiuk, T. Kaler, G. Odor, D. Budden, A. Zlateski, N. Shavit A Multicore Path to Connectomics-on-Demand . PPoPP 2017 (Best Paper Nominee), Austin, Texas, USA
- P. Felber, S. Issa, A. Matveev, P. Romano Hardware Read-Write Lock Elision. EuroSys 2016, London, UK
- A. Matveev, N. Shavit, P. Felber, P. Marlier Read-Log-Update: A Lightweight Synchronization Mechanism for Concurrent Programming. SOSP 2015, Monterey, California, USA
- Y. Afek, A. Matveev, O. R. Moll, N. Shavit Amalgamated Lock-Elision. DISC 2015, Tokyo, Japan
- D. Alistarh, W. M. Leiserson, A. Matveev, N. Shavit ThreadScan: Automatic and Scalable Memory Reclamation. SPAA 2015, Portland, Oregon, USA
- A. Matveev, N. Shavit Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory. ASPLOS 2015, Istanbul, Turkey
- Y. Afek, A. Matveev, N. Shavit Reduced Hardware Lock Elision. WTTM 2014, Paris, France
- D. Alistarh, P. Eugster, M. Herlihy, A. Matveev, N. Shavit StackTrack: An Automated Transactional Approach to Concurrent Memory Reclamation. EuroSys 2014, Amsterdam, The Netherlands
- D. Alistarh, J. Kopinsky, A. Matveev, N. Shavit The LevelArray: A Fast, Practical Long-Lived Renaming Algorithm ICDCS 2014, Madrid, Spain
- A. Matveev, N. Shavit Reduced Hardware NOREC: An Opaque Obstruction-Free and Privatizing HyTM. TRANSACT 2014, Salt Lake City, Utah, USA
- Y. Afek, A. Matveev, N. Shavit, Amalgamated Transactions: Executing Long Transactions Mostly in Hardware. Compiler, Architecture and Tools Conference 2013, Intel, Haifa, Israel
- A. Matveev, N. Shavit Reduced Hardware Transactions: A New Approach to Hybrid Transactional Memory. SPAA 2013, Montreal, Canada
- Y. Afek, A. Matveev, N. Shavit Pessimistic Software Lock-Elision. DISC 2012, Salvador, Brazil
- A. Matveev, N. Shavit Towards a Fully Pessimistic STM Model. TRANSACT 2012, New Orleans, LA, USA
- D. Dice, A. Matveev, and N. Shavit, Implicit Privatization Using Private Transactions. TRANSACT 2010, Paris, France
- A. Matveev, O. Shalev, and N. Shavit. Dynamic Identification of Transactional Memory Locations. Technical Report. Tel-Aviv University. 2009.