MIT Room 32G-844
I am an Edwin Sibley Webster Professor of
Electrical Engineering and Computer Science
Computer Science and Artificial Intelligence Laboratory (CSAIL).
I belong to the Computation Structures Group.
My research interests include computer architecture, computer security, VLSI design, computer-aided design, hardware validation, network router hardware, and computational biology.
One project I was involved with was building Aegis, a secure hardware processor that uses Physical Unclonable Functions (PUFs) to generate secret keys from chip fabrication variations. PUFs can also be used for low-cost authentication. This Canon camera bought in 2014 can be authenticated using an NFC-enabled phone because the package has an RFID PUF tag (black box marked Canon) on it. Contrast the tag with the first silicon PUF built during 2002-04 at MIT!
In 2013, my group fabricated EM2, a 110-core Execution Migration Machine, a 10mm x 10mm, 357,000,000 transistor chip in 45nm technology. EM2 uses deadlock-free computation migration to provide a shared memory abstraction without requiring directories and uses an intelligent predictor to determine when to migrate computation versus data and what part of the context to migrate. You can read about our design experience here. Chip die photo and EM2 board!
My research group has designed Ascend, a new type of secure processor that allows untrusted programs to compute on encrypted data from a client without leaking information about the data. Ascend uses Path ORAM with optimizations and integrity verification to obfuscate memory address patterns. Ascend also protects the timing channel. Ascend was integrated with the Princeton Piton multicore processor and was taped out in 32nm technology in March 2015. The chip is 6mm x 6mm and contains more than 600,000,000 transistors!
We recently came up with a time traveling coherence protocol called Tardis which has the unique feature that it does not require multicast or a globally synchronized clock, and only requires O(log N) storage in an N-core system.
I am also interested in the scaling of databases and data management systems to 1000-core processors.
I am the Computer Science track coordinator of the MIT PRIMES high-school outreach program, a year-long program where high-school students are exposed to research and mentored by MIT students. I am an EECS oversight officer for the 6-7 undergraduate and 6-7 MEng program.
I served as the chair of Area II (Computer Science Graduate Program) from June 2003 to November 2005, and as the Research Director of Architecture, Systems and Networking within CSAIL from September 2003 to October 2005. I served as Associate Head of the Department of Electrical Engineering and Computer Science with responsibility for Computer Science from 2005 to 2011.
|Computer Architecture.||Computer Security.||Computational Biology.|
|Architecture Exploration/Embedded Systems.||Compiler Optimization.||Design for Low Power Dissipation.|
|Boolean Representation.||Asynchronous Design.||Layout and Logic Synthesis.|
|Test Generation/Synthesis for Testability.||Formal and Semi-Formal Verification.||Network Routers.|
I have lectured or co-lectured several classes at MIT:
I have served as an advisor to several companies, including 0-in Design Automation (acquired by Mentor) and Sandburst Corporation (acquired by Broadcom), and Verayo.