Srini Devadas

    MIT Room 32G-844
    32 Vassar Street
    Cambridge, MA 02139
    U.S.A.
    devadas@mit.edu


I am an Edwin Sibley Webster Professor of Electrical Engineering and Computer Science at MIT in the Computer Science and Artificial Intelligence Laboratory (CSAIL). I belong to the Computation Structures Group.

My current research interests are primarily in the areas of computer architecture and computer security.

One project I was involved with was building Aegis, a secure hardware processor that uses Physical Unclonable Functions (PUFs) to generate secret keys from chip fabrication variations. Xilinx Zynq Ultrascale+ FPGAs use PUFs to generate secret keys.

PUFs can also be used for low-cost authentication. This Canon camera bought in 2014 can be authenticated using an NFC-enabled phone because the package has an RFID PUF tag (black box marked Canon) on it. Contrast the tag with the first silicon PUF built during 2002-04 at MIT!

In 2013, my group fabricated EM2, a 110-core Execution Migration Machine, a 10mm x 10mm, 357,000,000 transistor chip in 45nm technology. EM2 uses deadlock-free computation migration to provide a shared memory abstraction without requiring directories and uses an intelligent predictor to determine when to migrate computation versus data and what part of the context to migrate. You can read about our design experience. Chip die photo and EM2 board!

My research group designed Ascend, a new type of secure processor that allows untrusted programs to compute on encrypted data from a client without leaking information about the data. Ascend uses Path ORAM with optimizations and integrity verification to obfuscate memory address patterns. Ascend also protects the timing channel. Ascend was integrated with the Princeton Piton multicore processor and taped out in 32nm technology in March 2015. The chip is 6mm x 6mm, contains more than 460,000,000 transistors and runs at 500MHz!

My group recently produced a detailed analysis of Intel SGX and used this knowledge to design Sanctum, a processor that is resistant to a broader class of software attacks than SGX and whose security is easier to analyze. We plan to release an open-source Sanctum based on the RISC-V in 2017.

We came up with a time traveling coherence protocol called Tardis which has the unique feature that it does not require multicast or a globally synchronized clock, and only requires O(log N) storage in an N-core system. Tardis can be generalized to relaxed consistency models.

I am interested in the scaling of databases and data management systems to 1000-core processors, and concurrency control for databases.

Recently, my group pointed out vulnerabilities in anonymizing networks, and designed Riffle, a system with strong anonymity.


I am the Computer Science track coordinator of the MIT PRIMES high-school outreach program, a year-long program where high-school students are exposed to research and mentored by MIT students. I am an EECS oversight officer for the 6-7 undergraduate and 6-7 MEng program.

I served as the chair of Area II (Computer Science Graduate Program) from June 2003 to November 2005, and as the Research Director of Architecture, Systems and Networking within CSAIL from September 2003 to October 2005. I served as Associate Head of the Department of Electrical Engineering and Computer Science with responsibility for Computer Science from 2005 to 2011.


Selected Publications

Computer Architecture. Computer Security. Database Management.
Computational Biology. Architecture Exploration/Embedded Systems. Compiler Optimization.
Design for Low Power Dissipation. Boolean Representation. Asynchronous Design.
Layout and Logic Synthesis. Test Generation/Synthesis for Testability. Formal and Semi-Formal Verification.


Teaching

I have taught several classes at MIT:

Fundamentals of Programming (6.S04), Fall 2015, Spring 2016.
Introduction to Computer Science and Programming (6.00), Spring 2012, Fall 2013.
Computer and Network Security (6.857), Spring 2010.
Elements of Software Construction (6.005), Spring 2009, Fall 2010, Spring 2011.
Design and Analysis of Algorithms (the new 6.046), Fall 2008, Fall 2012, Spring 2015 OCW Version.
Introduction to Algorithms (6.006), Fall 2007, Spring 2008, Fall 2009, Fall 2011 OCW Version, Spring 2014.
Introduction to Algorithms (the old 6.046), Spring 2007.
Recitations in Digital Communication Systems (6.02), Fall 2014.
Laboratory in Software Engineering (6.170), Fall 2001, Spring 2002, Fall 2003, Fall 2005.
Computer Architecture (6.823), Spring 2002, Fall 2009.
Mathematics for Computer Science (6.042), Fall 1998, Fall 2000, Spring 2003, Spring 2005 OCW Version.
Computation Structures (6.004), Spring 2004, Fall 2006. Teaching material from Fall 1996/Spring 1998 terms.
Recitations in 6.001: Structure and Interpretation of Computer Programs, Fall 2004.
Recitations in 6.033: Computer Systems Engineering, Spring 2013.
Computer-Aided Design of Integrated Circuits (6.373), Spring 1989, Spring 1991-3-5-7, Spring 1999.
Introduction to VLSI Systems (6.371), Fall 1989, Spring 1990, Fall 1991, Fall 1994-5, Fall 1997.
Formal Verification in VLSI Design (6.892), Fall 1992.
Recitation sections in 6.002: Circuits and Electronics, Fall 1988.


Srini Devadas
MIT CSAIL
32-G844, 32 Vassar Street
Cambridge, MA 02139
(617) 253 0454
(617) 253 6652 (Fax)
devadas@mit.edu