MIT Room 32G-844
I am an Edwin Sibley Webster Professor of
Electrical Engineering and Computer Science
Computer Science and Artificial Intelligence Laboratory (CSAIL).
I belong to the Computation Structures Group.
My research interests include computer architecture, computer security, VLSI design, computer-aided design, hardware validation, network router hardware, and computational biology.
One project I was involved with was building Aegis, a secure hardware processor that uses Physical Unclonable Functions (PUFs) to generate secret keys from chip fabrication variations. My research group has worked on trusted virtual computation and secure virtual storage as part of the Quanta Qumulus project at MIT.
My group has worked on novel on-chip networks and routing algorithms. We recently fabricated EM2, a 110-core Execution Migration Machine, a 10mm x 10mm, 357,000,000 transistor chip in 45nm technology. EM2 uses deadlock-free computation migration to provide a shared memory abstraction without requiring directories and uses an intelligent predictor to determine when to migrate computation versus data. You can read about our design experience here. Chip die photo and EM2 board!
I was also involved in the Angstrom project. Angstrom is a proposed 1000-core self-aware processor. We built an Angstrom energy-aware processor tile in 0.18um with a LEON3 processor and energy monitors that allow software to precisely monitor energy consumption. Large-scale multicores may require locality-aware coherence and locality-aware replication in the Last Level Cache.
My research group is designing Ascend, a new type of secure processor that allows untrusted programs to compute on encrypted data from a client without leaking information about the data. Ascend uses Path ORAM with optimizations and integrity verification to obfuscate memory address patterns. Ascend also protects the timing channel and has been extended to stream programs.
I am the Computer Science track coordinator of the MIT PRIMES high-school outreach program, a year-long program where high-school students are exposed to research and mentored by MIT students. I am an EECS oversight officer for the 6-7 undergraduate and 6-7 MEng program.
I served as the chair of Area II (Computer Science Graduate Program) from June 2003 to November 2005, and as the Research Director of Architecture, Systems and Networking within CSAIL from September 2003 to October 2005. I served as Associate Head of the Department of Electrical Engineering and Computer Science with responsibility for Computer Science from 2005 to 2011.
|Computer Architecture.||Computer Security.||Computational Biology.|
|Architecture Exploration/Embedded Systems.||Compiler Optimization.||Design for Low Power Dissipation.|
|Boolean Representation.||Asynchronous Design.||Layout and Logic Synthesis.|
|Test Generation/Synthesis for Testability.||Formal and Semi-Formal Verification.||Network Routers.|
I have lectured or co-lectured several classes at MIT:
I have served as an advisor to several companies, including 0-in Design Automation (acquired by Mentor) and Sandburst Corporation (acquired by Broadcom), and am currently serving on Verayo's board.