SIMSYNCH is a simulator for digital electronics at scales from chip to
The design files are comprised of Scheme definitions and expressions.
These design files can be run as a Scheme program at high speed. The
design files can also be translated into formats suitable for logic
compilers (MACHXL and Verilog).
SIMSYNCH is an application of the SCM Scheme
SIMSYNCH simulates blocks of synchronous logic, signals whose states
change simultaneously on a clock signal transition. Each block also
has a reset signal, which forces all signals to the state specified
in the design file. SIMSYNCH can simultaneously simulate multiple
blocks with different clocks and resets. Devices can contain
multiple blocks; Blocks can span multiple devices.
Included in the SimSynch distribution is fifo8, a trivial design example of an 8-word FIFO
with a testbench demonstrating its operation. The transcript shows 8 bytes being written to the
empty FIFO from cycle 05 through cycle 0c; and 8 bytes are read from
cycles 19 through 20. Several files are generated by by running
- test_fifo.vhd is the VHDL translation
of the FIFO block.
- test_stim.vhd is the VHDL translation
of the testbench.
- fifo8-spew.dat is a data file of
stimulus inputs to the VHDL simulation and expected output values to
verify correct VHDL translation.
- wave.do sets up the "wave" timing display
of ModelTech simulation.
- SLIB Scheme Library
- SCM Scheme Implementation
Copyright © 1995, 1996, 1997, 1998, 1999, 2000, 2001,
2002, 2003, 2005, 2007, 2008, 2010 Aubrey Jaffer
- FTP Links to SIMSYNCH and related
software from this site and mirrors.
- htmls.zip, a collection of these html
documentation files (600.kB)
I am a guest and not a member of the MIT Computer Science and Artificial Intelligence Laboratory.
My actions and comments do not reflect in any way on MIT.|
|agj @ alum.mit.edu