Computer Architecture

N. Samardzic, S. Langowski, S. Devadas, and D. Sanchez, "Accelerating Zero-Knowledge Proofs Through Hardware-Algorithm Co-Design", Proceedings of the 57th International Symposium on Microarchitecture (MICRO), November 2024. Nominated for the Best Paper Award.

S. Devadas, S. Langowski, N. Samardzic, S. Servan-Schreiber, and D. Sanchez, "Designing Hardware for Cryptography and Cryptography for Hardware", Proceedings of the Computer and Communication Security Conference , November 2022. Invited Keynote Slides.

N. Samardzic, A. Feldmann, A. Krastev, N. Manohar, N. Genise, S. Devadas, K. Eldafrawy, C. Peikert, and D. Sanchez, "CraterLake: A Hardware Accelerator for Efficient Unbounded Computation on Encrypted Data", Proceedings of the 49th International Symposium on Computer Architecture, June 2022.

N. Samardzic, A. Feldmann, A. Krastev, S. Devadas, R. Dreslinski, C. Peikert, and D. Sanchez, "An Architecture to Accelerate Computation on Encrypted Data", IEEE Micro Top Picks in Computer Architecture, April/May 2022.

N. Samardzic, A. Feldmann, A. Krastev, S. Devadas, R. Dreslinski, C. Peikert, and D. Sanchez, "F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption", Proceedings of the 54th Symposium on Microarchitecture, October 2021. IEEE Micro Top Picks 2022.

B. Plancher, S. Neuman, T. Bourgeat, S. Kiundersma, S. Devadas, and V. Janapa Reddi, "Accelerating Robot Dynamics Gradients on a CPU, GPU, and FPGA", Proceedings of the 2021 IEEE International Conference on Robotics and Automation (ICRA), May 2021.

S. Neuman, B. Plancher, T. Bourgeat, T. Tambe, S. Devadas, and V. Janapa Reddi, "Robomorphic Computing: A Design Methodology for Domain-Specific Accelerators Parameterized by Robot Morphology", Proceedings of the 2021 Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2021. Honorable Mention, IEEE Micro Top Picks 2022.

S. Neuman, T. Koolen, J. Drean, J. E. Miller, and S. Devadas, "Benchmarking and Workload Analysis of Robot Dynamics Algorithms", Proceedings of the 2019 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), November 2019.

T. Bourgeat, I. Lebedev, A. Wright, S. Zhang, Arvind, and S. Devadas, "MI6: Secure Enclaves in a Speculative Out-of-Order Processor", Proceedings of the 52nd Symposium on Microarchitecture, October 2019.

I. Lebedev, K. Hogan, J. Drean, D. Kohlbrenner, D. Lee, K. Asanovic, D. Song and S. Devadas, "Sanctorum: A Lightweight Monitor for Secure Enclaves", Proceedings of the Design Automation and Test in Europe (DATE) Symposium, March 2019.

V. Kiriansky, I. Lebedev, S. Amarasinghe, S. Devadas, and J. Emer, "DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors", Proceedings of the 51st Symposium on Microarchitecture, October 2018.

I. Lebedev, K. Hogan, and S. Devadas, "Secure Boot and Remote Attestation in the Sanctum Processor", Proceedings of the 31st Computer Security Foundations Symposium, July 2018. Invited Keynote.

S. Neuman, J. Miller, D. Sanchez, and S. Devadas, "Using Application-Level Thread Progress Information to Manage Power and Performance", Proceedings of the International Conference on Computer Design, November 2017.

P. Subramanyan, R. Sinha, I. Lebedev, S. Devadas and S. Seshia, "A Formal Foundation for Secure Remote Execution of Enclaves", Proceedings of the Computer and Communication Security Conference, October 2017. Best Paper Award.

X. Yu, C. Hughes, N. Satish, O. Mutlu, and S. Devadas, "Banshee: Bandwidth-Efficient DRAM Caching Via Software Hardware Cooperation", Proceedings of the 50th International Symposium on Microarchitecture, October 2017.

V. Costan, I. Lebedev, and S. Devadas, "Secure Processors Part II: Intel SGX Security Analysis and MIT Sanctum Architecture", Foundations and Trends in Electronic Design Automation, Volume 11, Number 3, July 2017.

V. Costan, I. Lebedev, and S. Devadas, "Secure Processors Part I: Background, Taxonomy for Secure Enclaves and Intel SGX Architecture", Foundations and Trends in Electronic Design Automation, Volume 11, Number 1-2, July 2017.

L. Ren, C. Fletcher, A. Kwon, M. van Dijk, and S. Devadas, "Design and Implementation of the Ascend Secure Processor", IEEE Transactions on Dependable and Secure Computing, online publication, March 2017. Appeared in the March/April 2019 issue.

X. Yu, H. Liu, E. Zou, and S. Devadas, "Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models", Proceedings of the 25th International Conference on Parallel Architectures and Compilation Techniques, September 2016. Contributions from MIT PRIMES students.

V. Costan, I. Lebedev, and S. Devadas,"Sanctum: Minimal Hardware Extensions for Strong Software Isolation", Proceedings of the 25th Usenix Security Symposium, August 2016. Slides with notes.

X. Yu, C. Hughes, N. Satish, and S. Devadas, "IMP: Indirect Memory Prefetcher", Proceedings of the 48th International Symposium on Microarchitecture, December 2015.

G. Kurian, Q. Shi, S. Devadas, and O. Khan, "OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access", Proceedings of the 24th International Conference on Parallel Architectures and Compilation Techniques, October 2015.

X. Yu, and S. Devadas, "Tardis: Time Traveling Coherence Algorithm for Distributed Shared Memory", Proceedings of the 24th International Conference on Parallel Architectures and Compilation Techniques, October 2015. Presented in the Best Paper Session.

K. S. Shim, M. Lis, O. Khan, and S. Devadas, "The Execution Migration Machine: Directoryless Shared Memory Architecture", IEEE Computer, September 2015.

X. Yu, S. K. Haidar, L. Ren, C. Fletcher, A. Kwon, M. van Dijk, S. Devadas, "PrORAM: Dynamic Prefetcher for Oblivious RAM", International Symposium on Computer Architecture (ISCA), June 2015.

C. Fletcher, L. Ren, A. Kwon, M. van Dijk, E. Stefanov, D. Serpanos, S. Devadas, "A Low-Latency, Low-Area Hardware ORAM Controller", Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2015.

C. . Fletcher, L. Ren, A. Kwon, M. van Dijk, S. Devadas, "Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM", Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015.

X. Yu, G. Bezerra, A. Pavlo, S. Devadas, and M. Stonebraker, "Staring into the Abyss: An Evaluation of Concurrency Control with One Thousand Cores", Proceedings of the VLDB Endowment, November 2014.

Y. Sinangil, S. Neuman, M. E. Sinangil, N. Ickes, G. Bezerra, E. Lau, J. Miller, H. Hoffmann, S. Devadas, and A. Chandrakasan, "A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation", Proceedings of the 2014 Symposium on VLSI Circuits, June 2014.

G. E. Suh, C. Fletcher, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas, "Author Retrospective: AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing", International Conference on Supercomputing 25th Anniversary Volume, 2014.

G. E. Suh, G. Kurian, S. Devadas, and L. Rudolph, "Author Retrospective: Analytical Cache Models With Applications to Cache Partitioning", International Conference on Supercomputing 25th Anniversary Volume, 2014.

G. Kurian, S. Devadas, and O. Khan, "Locality-Aware Data Replication in the Last Level Cache", Proceedings of the High Performance Computer Architecture conference (HPCA), February 2014.

C. Fletcher, L. Ren, X. Yu, M. van Dijk, O. Khan, and S. Devadas, "Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs", Proceedings of the Int'l Symposium on High Peformance Computer Architecture (HPCA), February 2014.

K. S. Shim, M. Lis, M. H. Cho, I. Lebedev, and S. Devadas, "Design Tradeoffs for Simplicity and Efficient Verification in the Execution Migration Machine", Proceedings of the Int'l Conference on Computer Design, October 2013. Invited Keynote.

C. Fletcher, R. Harding, O. Khan, and S. Devadas, "A Framework to Accelerate Sequential Programs on Homogeneous Multicores", Proceedings of the 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SoC), October 2013.

L. Ren, X. Yu, C. Fletcher, M. van Dijk, and S. Devadas, "Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors", Proceedings of the Int'l Symposium on Computer Architecture (ISCA), June 2013.

G. Kurian, O. Khan, and S. Devadas, "The Locality-Aware Adaptive Cache Coherence Protocol", Proceedings of the Int'l Symposium on Computer Architecture (ISCA), June 2013.

C. Fletcher, M. van Dijk, and S. Devadas, "Let's Stop Trusting Software With Our Sensitive Data", IEEE Design and Test of ICs, March/April 2013. The Last Byte.

M. Kinsy, M. H. Cho, K. S. Shim, M. Lis, G. E. Suh, and S. Devadas, "Optimal and Heuristic Application-Aware Oblivious Routing", IEEE Transactions on Computers, January 2013.

C. Fletcher, M. van Dijk, and S. Devadas, "A Secure Processor Architecture for Encrypted Computation on Untrusted Programs", ACM Scalable Trusted Computing Workshop (STC), October 2012.

K. S. Shim, M. Lis, O. Khan, and S. Devadas, "Thread Migration Prediction for Distributed Shared Caches", Computer Architecture Letters, September 2012.

P. Ren, M. Lis, M. H. Cho, K. S. Shim, C. W. Fletcher, O. Khan, N. Zheng, and S. Devadas, "HORNET: A Cycle-Level Multicore Simulator", IEEE Transactions on Computer-Aided Design, June 2012.

H. Hoffmann, J. Holt, G. Kurian, E. Lau, M. Maggio, J. E. Miller, S. M. Neuman, M. Sinangil, Y. Sinangil, A. Agarwal, A. P. Chandrakasan, S. Devadas, "Self-aware Computing in the Angstrom Processor", Proceedings of the 49th Design Automation Conference (DAC), June 2012.

K. S. Shim, M. Lis, O. Khan, and S. Devadas, "Judicious Thread Migration When Accessing Distributed Shared Caches", Third Workshop on Computer Architecture and Operating System co-design (CAOS), January 2012.

M. Lis, K. S. Shim, M. H. Cho, O. Khan, and S. Devadas, "Directoryless Shared Memory Coherence Using Execution Migration", Proceedings of the IASTED International Conference on Parallel and Distributed Computing, December 2011. Best Paper Award.

M. Lis, K. S. Shim, M. H. Cho, and S. Devadas, "Memory coherence in the age of multicores", Proceedings of the Int'l Conference on Computer Design, October 2011. Invited Keynote.

O. Khan, H. Hoffmann, M. Lis, F. Hijaz, A. Agarwal, and S. Devadas, "ARCc: A Case for an Architecturally Redundant Cache-coherence Architecture for Large Multicores", Proceedings of the Int'l Conference on Computer Design, October 2011.

M. Lis, K. S. Shim, M. H. Cho, C. Fletcher, M. Kinsy, I. Lebedev, O. Khan, and S. Devadas, "Brief Announcement: Distributed Shared Memory based on Computation Migration", Proceedings of the 23rd Symposium on Parallelism in Algorithms and Architectures (SPAA), June 2011.

M. H. Cho, K. S. Shim, M. Lis, O. Khan, and S. Devadas, "Deadlock-Free Fine-Grained Thread Migration", Proceedings of the 5th Network-on-Chip Symposium (NOCS), May 2011. Best Paper Award.

M. Lis, P. Ren, M. H. Cho, K. S. Shim, C. Fletcher, O. Khan, and S. Devadas, "Scalable Accurate Multicore Simulation in the 1000 core era", IEEE International Symposium on Performance Analysis of Systems and Software, April 2011.

M. Lis, K. S. Shim, O. Khan, and S. Devadas, "Shared Memory via Execution Migration", ASPLOS Ideas and Perspectives Session, March 2011.

O. Khan, M. Lis, Y. Sinangil, and S. Devadas, "DCC: A Dependable Cache Coherence Multicore Architecture", Computer Architecture Letters, February 2011.

K. S. Shim, M. H. Cho, M. Lis, O. Khan, and S. Devadas, "System-level Optimizations for Memory Access in the Execution Migration Machine (EM²)", Second Workshop on Computer Architecture and Operating System co-design (CAOS), January 2011.

H. Hoffmann, S. Devadas, and A. Agarwal, "A pattern for efficient parallel computation on multicore processors with scalar operand networks", Proceedings of the 2010 Workshop on Parallel Programming Patterns (ParaPLoP '10), June 2010.

M. Lis, K. S. Shim, M. H. Cho, P. Ren, O. Khan, and S. Devadas, "Darsim: A Parallel Cycle-Level NoC Simulator", MOBS-6: Sixth Annual Workshop on Modeling, Benchmarking and Simulation, June 2010.

O. Khan, M. Lis, and S. Devadas, "Instruction-Level Execution Migration", CSAIL Technical Report TR-2010-019, April 2010.

M. Lis, M. H. Cho, K. S. Shim, and S. Devadas, "Path-Diverse Inorder Routing", Proceedings of the International Conference on Green Circuits and Systems, June 2010.

M. H. Cho, M. Lis, K. S. Shim, M. Kinsy, and S. Devadas, "Path-Based, Randomized, Oblivious Routing", Proceedings of the 2nd International Workshop on Network-on-Chip Architectures (NoCArc'09), December 2009.

H. Hoffmann, A. Agarwal, and S. Devadas, "Partitioning Strategies for Concurrent Programming", Proceedings of the IASTED International Conference on Parallel and Distributed Computing, October 2009.

M. H. Cho, M. Lis, M. Kinsy, K. S. Shim, T. Wen, and S. Devadas, "Oblivious Routing in On-Chip Bandwidth-Adaptive Networks", Proceedings of the PACT 2009 Conference, September 2009.

M. Lis, M. H. Cho, K. S. Shim, and S. Devadas, "Guaranteed in-order packet delivery using Exclusive Dynamic Virtual Channel Allocation", CSAIL Technical Report TR-2009-036, August 2009.

M. Kinsy, M. H. Cho, T. Wen, G. E. Suh, M. van Dijk and S. Devadas, "Application-Aware Deadlock-Free Oblivious Routing", Proceedings of the Int'l Symposium on Computer Architecture (ISCA), June 2009.

K S. Shim, M. H. Cho, M. Kinsy, T. Wen, M. Lis, G. E. Suh, and S. Devadas, "Static Virtual Channel Allocation in Oblivious Routing", Proceedings of the 3rd Network-on-Chip Symposium (NOCS), May 2009.

M. H. Cho, M. Kinsy, C-C. Cheng, G. E. Suh, and S. Devadas, "Diastolic Arrays: Throughput-Driven Reconfigurable Computing", Proceedings of the Int'l Conference on Computer-Aided Design, November 2008.

G. E. Suh, C. W. O'Donnell, and S. Devadas, "Aegis: A Single-Chip Secure Processor" , IEEE Design and Test Magazine, November 2007.

G. E. Suh, C. W. O'Donnell, and S. Devadas, "Aegis: A Single-Chip Secure Processor" , Elsevier Information Security Technical Report, August 6, 2005.

G. E. Suh, C. W. O'Donnell, I. Sachdev, and S. Devadas, "Design and Implementation of the AEGIS Secure Processor Using Physical Random Functions" , Proceedings of the Int'l Symposium on Computer Architecture, June 2005.

G. E. Suh, J-W. Lee, D. Zhang, and S. Devadas, "Secure program execution via dynamic information flow tracking", Proceedings of ASPLOS 2004, October 2004. Most Influential Paper Award (2014).

E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas, "Efficient Memory Integrity Verification and Encryption for Secure Processors", Proceedings of the 36th International Symposium on Microarchitecture (MICRO), December 2003.

E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas, "AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing", Proceedings of the 17th International Conference on Supercomputing, June 2003. Selected for inclusion in "25 Years of the International Conference on Supercomputing", 2014. Inaugural Intel Hardware Security Test of Time Award, 2022.

B. Gassend, E. Suh, D. Clarke, M. van Dijk, and S. Devadas, "Caches and Merkle Trees for Efficient Memory Authentication", Proceedings of the 9th High Performance Computer Architecture Symposium, February 2003.

G. Edward Suh, L. Rudolph, and S. Devadas, "Dynamic Partitioning of Shared Cache Memory", Journal of Supercomputing, 2002.

G. Edward Suh, S. Devadas, and L. Rudolph, "A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning", Proceedings of the High Performance Computer Architecture (HPCA'02) Conference, February 2002.

Prabhat Jain, S. Devadas, D. Engels, and L. Rudolph, "Software-Assisted Cache Replacement Mechanisms for Embedded Systems", Proceedings of the Int'l Conference on Computer-Aided Design, November 2001.

G. Edward Suh, L. Rudolph, and S. Devadas, "Effects of Memory Performance on Parallel Job Scheduling", Proceedings of the Job Scheduling Workshop, LNCS 2221, July 2001.

G. Edward Suh, L. Rudolph, and S. Devadas, "Dynamic Cache Partitioning for Simultaneous Multithreading Systems", Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS2001), August 2001. Best Paper Award.

G. Edward Suh, S. Devadas, and L. Rudolph, "Analytical Cache Models with Application to Cache Partitioning", Proceedings of the 15th International Conference on Supercomputing, June 2001. Selected for inclusion in "25 Years of the International Conference on Supercomputing", 2014.

D. Chiou, P. Jain, S. Devadas, and L. Rudolph, "Application-Specific Memory Management in Embedded Systems Using Software-Controlled Caches ", Proceedings of the 37th Design Automation Conference , June 2000.